This application claims the priority of Korean Patent Application No. 10-2004-0000908 filed on Jan. 7, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates generally to a package circuit board and a package including the package circuit board and method thereof, and more particularly, to a package circuit board including microelectronic chips mounted on a semiconductor substrate and a package including the package circuit board and method thereof.
2. Description of the Related Art
In the field of semiconductors, chip sizes may generally decrease while the operating speed (i.e., frequency) of electronic devices may generally increase. Thus, a current conventional package may be lighter, thinner, shorter, and/or smaller than an earlier constructed conventional package.
In conventional devices operating at lower speeds, electrical characteristics may not be considered to be factors in determining device performance. However, with the increase in the operating speed of chips, electrical characteristics of the packages may be a factor in achieving higher speeds of operation.
Electrical characteristics of package pins may also be a factor in achieving higher speeds of operation. Package pins may electrically connect chips on the package to external circuits. Various conventional package structures have been proposed with regard to the structure and arrangement of package pins.
A conventional chip package for operation at lower speeds of operation may include a lead frame and a plurality of pins which may be arranged along one side of the package. The plurality of pins may be spaced apart from one another at regular intervals. The plurality of pins may further be disposed along one side of the package in a one-dimensional arrangement using the lead frame.
However, as conventional packages are reduced in size, there may be a limitation to the maximum number of mountable pins. Further, electrical characteristics of chips for higher speeds of operation may degrade due to this limitation to the maximum number of mountable pins. The electrical characteristics may include an inductance, a capacitance and/or a resistance between the lead frame and at least one of a plurality of bonding wires within the chip. Thus, the above-described packaging technique may not be suitable for use in chips at higher speeds of operation.
Conventional chip scale packages have been proposed in order to overcome the above-described deficiency with respect to conventional packages. The conventional chip scale packages may allow a reduced package size for chips at higher speeds of operation.
The conventional chip scale package may include a plurality of pins and/or solder balls which may be arranged on at least one surface of a package in a two-dimensional matrix type. The chip scale package may reduce parasitic electric components of the pins and/or the solder balls as compared to the above-described conventional package using the lead frame. Thus, the conventional chip scale package may be suitable for use in both smaller sized and/or higher speed chips.
A conventional ball grid array (BGA) package may include a wafer, microelectronic chips mounted on a first surface of the wafer, and input/output (I/O) pins (i.e., solder balls) which may be formed on a second surface of the wafer. The I/O pins may be electrically connected to at least one microelectronic chip. The microelectronic chips may be supported by the wafer and connected to the I/O pins through the wafer.
In conventional chip scale packages, the package size may be reduced in order to keep pace with the reduced size of microelectronic chips mounted thereon. The number of I/O pins (i.e., the number of solder balls) may be a factor affecting the size of the conventional chip scale package. Since a microelectronic chip may require a reduced number of I/O pins (i.e., solder balls), the reduction of the size of the conventional chip scale packages may be limited and dependent upon the limited number of I/O pins.